The present invention is directed to semiconductor devices and, more specifically, to thyristor-based semiconductor devices, such as thyristor-based memory devices and other thyristor-based current-switching circuits.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2,where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F2 and 100 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noisc-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for thyristor-based applications. An important consideration in the design of the thin capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Another important consideration in semiconductor device design, including those employing thin capacitively coupled thyristor-type devices and memory implementations, includes forming devices in a very dense array. In order to achieve such a dense array, it is sometimes desirable to form trenches having a very high aspect ratio (the ratio of height to width of the opening of the trench). Portions of the devices must be electrically insulated from other circuitry, however, and commonly used insulative materials are difficult to implement when filling trenches having high aspect ratios (e.g., greater than 2:1).
These and other design considerations have presented challenges to efforts to implement such a thin capacitively coupled thyristor in bulk substrate applications, and in particular to highly dense applications.
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in other memory cells. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a thyristor-based (i.e., thyristor-including) semiconductor device is manufactured having a substrate and a thyristor body, wherein at least one region of the thyristor body is in the substrate. A trench is provided in the substrate adjacent to the thyristor region in the substrate, and an insulative liner material is formed in the trench. A conductive material is formed in a portion of the lined trench laterally adjacent to the thyristor region in the substrate, with the insulative liner material electrically insulating the conductive material from the thyristor region in the substrate. A conductive thyristor control port is formed in the trench and adapted for capacitively coupling to the thyristor body. The thyristor body region in the substrate is arranged having a cross section such that the capacitive coupling of a voltage transition from the control port results in an outflow of minority carriers from the thyristor body region. The outflow of minority carriers switches the thyristor-based semiconductor device at least from a current-passing mode to a current-blocking mode for current flow between the opposite end regions of the thyristor body. With this approach, conductive material can be used to fill a trench portion that also electrically isolates part of the thyristor, and permits the manufacture of trenches having high aspect ratios. This approach is particularly useful in applications where forming insulative material in the trench is difficult due to the aspect ratio being relatively high.
In another example embodiment of the present invention, a memory arrangement includes a memory cell including the thyristor-based semiconductor device in the example embodiment discussed above. The thyristor includes anode and cathode end portions, each end portion having a base region electrically coupled to an emitter region, and each base region being electrically coupled to one another. The memory cell also includes a pass device having source/drain regions separated by a channel region and a gate capacitively coupled to the channel region. One of the source/drain regions is coupled in series with the thyristor at a first one of the emitter regions, and another one of the source/drain regions is coupled to a bit line. A first word line is adapted to apply a voltage to the gate of the pass device for controlling the current flow therein, where the pass device forms a conductive link between the bit line and the thyristor when the pass device is in a conducting state. A second word line is adapted to apply a voltage to the control port of the thyristor for controlling current flow therein, and a second one of the emitter regions is coupled to a conductor at a reference voltage.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.